Processor and Memory Architectures

Von Neumann

• Uses a shared memory region
• Has several security implications (e.g buffer overflow)
• Uses one bus for data and instruction

Harvard Architecture

• Uses separate memory regions for instructions (opcode) and data
• Provides parallel access
• Uses different bus for data and instruction
• x86s and ARM uses this

Harvard vs Von Neumman

• A method of memory management
• Enables each application to operate in its own memory space
• Allows multiple programs to access memory without interfering with one another’s data
• Allows extending physical memory size by putting sections of memory to secondary storage (e.g disk) to free up memory space
  • Page - fixed size memory sections that are being allocated or moved to secondary storage
  • Page swapping - process of moving pages
  • Swap file - contains the pages
• Access violation - attempts to access memory space not intended for you
• A memory page can be:
  • readonly
  • executable
  • shared (for interprocess communication)
• Example virtual-to-physical address translation in Windows NT

• Page Fault - transfer of control to OS to do address translation (virtual to physical address translation and vice versa; not really an error)
  • Soft Fault
  • Hard Fault - accessing a page that has been swapped to secondary storage
• Page status bits
• Page Frames
  • Contiguous 4KB section of Windows NT physical memory

Memory Pools

Example below are for Windows NT

• Non-paged pool - contains page frames that must remain resident in memory at all times (e.g for performance reaons)
• Paged pool - can be swapped out to disk
• PFN (Page Frame Number) database
  • Active
  • Standby
  • Modified
  • Free
  • Zeroed
  • Bad

Memory Management Unit (MMU)

• Processor component that controls memory allocation, address translation and protection functions
• Contains a cache - improves the speed of memory access by avoiding the need to traverse the page table directory and perform a page table lookup during each memory access

Each time the processor needs to access physical memory, which may occur multiple times during the execution of a single instruction, it first checks the TLB's associative memory to determine whether the translation information is resident in the TLB. If it is, the instruction immediately uses the information stored in the TLB to access physical memory. If the TLB does not contain the requested translation, a page fault occurs and the processor must traverse the page table directory and a page table to determine the translated address, assuming the referenced page is resident in memory.

• Other MMU functions
  • Separation of virtual memory into kernel space and user space
  • Isolation of process memory
  • Page-level access restrictions
  • Detection of software problems
• Null pointer exception - program error that tries to access invalid memory location (e.g $00000000)